The Xscale evaluation board would make a nice PC104 board for a wearable or other purposed. <http://developer.intel.com/design/iio/prodbref/80310.htm> Intel 80200 Processor 32-bit high-performance CPU (333, 466, 600, 733 MHz) based on Intel XScale[tm] Microarchitecture ARM* v.5TE compliant Intel Superpipelined RISC technology - high core speeds with low power 32 KB data and instruction caches 2 KB Mini data cache for accelerated streaming Intel 80312 I/O Companion Chip Integrated 64-bit, 66 MHz PCI-to-PCI bridge (PCI 2.2 compliant) 100 MHz internal bus for up to 800 Mbytes/second bandwidth Integrated Memory Controller supports 100 MHz SDRAM (up to 512 Mbytes) 1 KB programmable Application Accelerator Unit to speed parity generation Added feature integration: 6 secondary PCI output clocks, 4 SDRAM output clocks, 8 general-purpose I/O pins <http://developer.intel.com/design/iio/prodbref/iq80310.htm> Product Highlights of the "IQ80310 Software Development and Processor Evaluation Kit" Complete Intel IOP310 I/O chipset-based platform for rapid intelligent I/O software development JTAG HW Emulator IxWorks I2O-compatible RTOS by Wind River Systems Evaluation copy of VxWorks RTOS and Tornado development environment Evaluation copy of Linux RTOS Evaluation copy of ARM Developmen Suit Red Hat GNUPro Tools (no support package included) 64-bit or 32-bit, 66 MHz or 33 MHz, +3.3V or +5V primary PCI bus interface 64-bit or 32-bit, 66 MHz or 33 MHz, +3.3V secondary PCI bus connected to the primary PCI interface with a PCI-to-PCI bridge 2 PCI expansion slots available (secondary PCI bus) 2 Serial console ports based on 16C550 UART Ethernet debug ports based on the 82559 device Flash ROM, 8 Mbytes JTAG debug header and logic analyze connectors for bus and signal probing 168-pin, 3.3V DIMM socket supporting 32 to 512 Mbytes of Synchronous DRAM organized x72 to support Error Correction Code (ECC) and clocked at 100 MHz (Intel® IQ80310 is shipped with 32 Mbytes of SDRAM) Two user-programmable 7-segment displays 4 Indicator LEDs: processor has passed self-test, 3.3V is supplied to the platform, and 66 MHz is enable for the primary and the secondary PCI slots General purpose I/O header Battery backup circuit for SDRAM System hardware monitor device for temperature and on-board voltages DMA channels on both PCI buses FC Serial Bus Electronic manuals and documentation -- Subscription/unsubscription/info requests: send e-mail with subject of "subscribe", "unsubscribe", or "info" toWear-Hard Mailing List Archive (searchable): http://wearables.blu.org please, Please, *PLEASE* don't subscribe through a forward/false domain
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