I've been digging pretty deep into transmeta crusoe specs, and to be hone=
st,
I wasn't paying very much attention to it until recently. But it is indee=
d a
very interesting processor.
Actually, it's more that just a processor, it has a north bridge (64-bit =
CPU
bus to RAM) and dual RAM controllers right on the Crusoe chip. Those dual
RAM controllers are for DDR (double data rate) SDRAM and also for the nor=
mal
SDR SDRAM. The DDR SDRAM burns 50% less power while yielding 10-20%
performance increase over SDR SDRAM. Further, the Crusoe processor also h=
as
a PCI controller and south bridge interface right on the chip. If you
compare with pentiums for example, they need a lot more support circuitry=
,
the north and south bridges etc. Here is some technical info on the TM580=
0
...
Crusoe TM Processor Model TM5800 Features
=B0 VLIW processor and x86 Code Morphing TM software provide
x86-compatible mobile platform solution
=B0 Processors fabricated in latest 0.13 process technology
operate up to 800 MHz at very low power levels
=B0 Standard product speeds of 667, 700, 733, and 800 MHz
=B0 Integrated 64K-byte L1 instruction cache, 64K-byte L1
data cache, and 512K-byte L2 write-back cache
=B0 Integrated northbridge core logic features facilitate
compact system designs
=B0 DDR SDRAM memory controller with 100-133 MHz, 2.5V interface
=B0 SDR SDRAM memory controller with 100-133 MHz, 3.3V interface
=B0 PCI bus controller (PCI 2.1 compliant) with 33 MHz,
3.3V interface
=B0 LongRun TM advanced power management with ultra-low power
operation extends mobile battery life
=B0 0.4 - 1.0W @ 367-800 MHz, 0.9 - 1.3V running typical
multimedia applications
=B0 150 mW in deep sleep
=B0 Full System Management Mode (SMM) support
=B0 Compact 474-pin ceramic BGA package is fully pin-compatible
with existing TM5400 and TM5600 models
The Transmeta Crusoe processor is an ultra-low power, high-speed
microprocessor based on an advanced VLIW core architecture. When used in
conjunction with Transmeta's x86 Code Morphing software, the Crusoe
processor provides x86-compatible software execution using dynamic binary
code translation, without requiring code recompilation. In addition to th=
e
VLIW core, the processor incorporates separate 64K-byte instruction and d=
ata
caches, a large 512K-byte L2 write-back cache, 64-bit DDR SDRAM memory
controller, 64-bit SDR SDRAM memory controller, and 32-bit PCI con-trolle=
r.
These additional functional units, which are typically part of the core
system logic that surrounds the microproces-sor, allow the Crusoe process=
or
to provide a highly integrated and cost effective platform solution for t=
he
x86 mobile market. The processor core operates from a 0. 9-1. 3V supply,
resulting in extremely low power consumption, even at high operating
frequencies. With power consumption during typical operation as low as 15=
0
milliwatts, the Crusoe processor is the most energy efficient
high-performance x86-compatible mobile solution ever offered.
1.0 Architecture
The Crusoe processor incorporates integer and floating point execution
units, separate instruction and data caches, a level-2 write-back cache,
memory management unit, and
multimedia instructions. In addition to these traditional processor
features, the device integrates a DDR SDRAM memory controller, SDR SDRAM
memory controller, PCI bus controller and serial ROM interface controller.
These additional units are usually part of the core system logic that
surrounds the microprocessor. The VLIW processor, in combination with Cod=
e
Morphing software and the additional system core logic units, allow the
Crusoe processor to provide a highly integrated, ultra-low power, high
performance platform solution for the x86 mobile market.
2.0 Processor Core
The Crusoe processor core architecture is relatively simple by convention=
al
standards. It is based on a Very Long Instruction Word (VLIW) 128-bit
instruction set. Within this VLIW architecture, the control logic of the
processor is kept very simple and software is used to control the schedul=
ing
of instructions. This allows a simplified and very straightforward hardwa=
re
implementation with an in-order 7-stage integer pipeline and a 10-stage
floating point pipeline. By streamlining the processor hardware and reduc=
ing
the control logic transistor count, the performance-to-power consumption
ratio can be greatly improved over traditional x86 architectures.
The Crusoe processor includes a 64K-byte 8-way set-associative Level 1 (L=
1)
instruc-tion cache, and a 64K-byte 16-way set associative L1 data cache. =
The
TM5800 model also includes an integrated 512K-byte Level 2 (L2) write-bac=
k
cache for improved effective memory bandwidth and enhanced performance. T=
his
cache architecture assures maximum internal memory bandwidth for performa=
nce
intensive mobile appli-cations, while maintaining the same low-power
implementation that provides a superior performance-to-power consumption
ratio relative to previous x86 implementations. Other than having executi=
on
hardware for logical, arithmetic, shift, and floating point instructions,=
as
in conventional processors, the Crusoe processor has very distinctive
features from traditional x86 designs. To ease the translation process fr=
om
x86 to the core VLIW instruction set, the hardware generates the same
condition codes as conventional
x86 processors and operates on the same 80-bit floating point numbers. Al=
so,
the Translation Look-aside Buffer (TLB) has the same protection bits and
address mapping as x86 processors. The software component of this solutio=
n
is used to emulate all other features of the x86 architecture. The softwa=
re
that converts x86 programs into the core VLIW instructions is called Code
Morphing software. The combination of Code Mor-phing software and the VLI=
W
core together act as an x86-compatible solution.
The typical behavior of the Code Morphing software is to execute a loop
which decodes and executes x86 instructions. The first few times a specif=
ic
x86 code sequence is executed, Code Morphing interprets the code by decod=
ing
the instructions one byte at time and then dispatching execution to
corresponding VLIW native instruction subrou-tines. Once the x86 code has
been executed several times, Code Morphing translates the x86 instruction=
s
into highly optimized and extremely fast VLIW native instructions, execut=
es
the translated code, and caches the native instruction translations for
future use. If the same x86 code is required to execute again, the
high-performance cached translations are executed immediately and no
re-translation is required.
2.1 Integrated DDR SDRAM Memory Controller
The DDR SDRAM interface is the highest performance memory interface
available on the Crusoe processor. The DDR SDRAM controller supports only
Double Data Rate (DDR) SDRAM and transfers data at a rate that is twice t=
he
clock frequency of the inter-face. The DDR SDRAM controller supports up t=
o
two banks, the equivalent of two Dual In-line Memory Modules (DIMMs), of =
DDR
SDRAM using a 64-bit wide inter-face. The DDR SDRAM memory can be populat=
ed
with 64M-bit, 128M-bit, or 256M-bit devices. For highest performance, it =
is
recommended that the DDR SDRAM devices be soldered to the motherboard rat=
her
than incorporated on DIMMs. Also, to reduce signal loading, only x8 or x1=
6
devices should be used. The frequency setting for the DDR SDRAM interface=
is
initialized during the power-on boot sequence. Although the processor
supports a DDR interface frequency in the range of 1/2 to 1/15 of the cor=
e
frequency, the recommended interface frequency is between 100 and 133 MHz.
2.2 Integrated SDR SDRAM Memory Controller
The SDR SDRAM memory controller supports up to four banks, equivalent to =
two
Small Outline Dual In-line Memory Modules (SO-DIMMS), of Single Data Rate
(SDR) SDRAM that can be configured as 64-bit SO-DIMMs. These SO-DIMMs can=
be
popu-lated with 64M-bit, 128M-bit or 256M-bit devices. All SO-DIMMs must =
use
the same frequency SDRAMs, but there are no restrictions on mixing differ=
ent
SO-DIMM con-figurations into each SO-DIMM slot.
The frequency setting for the SDR SDRAM interface is initialized during t=
he
power-on boot sequence. Although the processor supports an SDR interface
frequency in the range of 1/2 to 1/15 of the core frequency, the recommen=
ded
interface frequency is between 100 and 133 MHz. It is also recommended th=
at
a maximum of 8 devices per SO-DIMM be used in order to operate at the
required frequency with the proper signal integrity.
2. 3 Integrated PCI Controller
The Crusoe processor includes a PCI bus controller that is PCI 2. 1
compliant. The PCI bus is 32 bits wide, operates at 33 MHz, and is
compatible with 3. 3V signal levels. It is not 5V tolerant, however. The =
PCI
controller on provides a PCI host bridge, the PCI bus arbiter, and a DMA
controller. The PCI bus can sustain 132 Mbytes/sec bursts for reads and
writes on 4K-byte blocks. The PCI controller snoops ahead on PCI-to-DRAM
reads and writes. The 16-Dword CPU-to-PCI write buffer converts sequentia=
l
memory mapped I/O writes to PCI bursts. The DMA controller handles
PCI-to-DRAM reads and writes. The 16-Dword PCI-to-DRAM write buffer conve=
rts
one 16-Dword burst to eight separate address/ data pairs. The 16-Dword
DRAM-to-PCI read ahead buffer permits continuation of read ahead activity
after hitting in the buffer. The PCI controller tri-states the PCI bus wh=
en
hot docking.
2.4 Serial ROM Interface
The Crusoe processor serial ROM interface is a five-pin interface used to
read data from a serial flash ROM. The flash ROM is 1M-byte in size and
provides non-volatile storage for the Code Morphing software. During the
boot process, the Code Morphing code is copied from the ROM to the Code
Morphing memory space in SDRAM. Once trans-ferred, the Code Morphing code
requires 16M-bytes of memory space. The portion of SDRAM space reserved f=
or
Code Morphing software is not visible to x86 code. Trans-meta supplies
programming information for the flash ROM device. This interface may also=
be
used for in-system reprogramming of the flash ROM.
3.0 Software Compatibility
When used in conjunction with Transmeta's x86 Code Morphing software, the
Crusoe processor provides x86-compatible software execution without
requiring code recompilation. Systems based on this solution are capable =
of
executing all standard x86-com-patible operating systems and applications=
,
including Microsoft Windows 9x, Windows ME, Windows 2000, and Linux.
4.0 Operating Power and Power Management
The Crusoe processor operates from a 0.9-1.3V core voltage supply at
extremely low power levels, even while the device is operating at very hi=
gh
performance. The TM5800 model incorporates LongRun adaptive power managem=
ent
technology. Lon-gRun power management dynamically reduces the core CPU po=
wer
consumption to near-optimal levels in response to processor work load
requirements. LongRun achieves this dynamic power reduction by varying th=
e
CPU clock and core power supply voltage in response to adaptive power
management protocols that
monitor processor load demands and control processor power and performanc=
e
levels. The Lon-gRun power management approach is particularly effective =
in
applications that run pre-dominantly
in the normal (active) power state, as described below. Additionally, the
Crusoe processor supports ACPI-compliant power management modes by
incorporating five distinct power states: Normal, Auto Halt, Quick Start,
Deep Sleep and Off. These power states may be used to reduce the operatin=
g
power of the processor during system states that require little or no CPU
activity.
Table 1 lists the recommended state of the processor for each of the ACPI
global system states. Typical power dissipation for each of the power sta=
tes
is shown in Table 2.
TABLE 1 Crusoe Processor Power Management System States
ACPI System State Processor DDR, SDR Clock
Power State SDRAM Generator
G0/S0 (Working) C0 Normal Normal Running
C1 Auto Halt Normal Running
C2 Quick Start Self Refresh Running
C3 Deep Sleep Self Refresh Clock Stopped
G1/S1 (Sleeping) Deep Sleep Self Refresh PLL Shut Down
G1/S2 (Suspend-to-RAM) Deep Sleep Self Refresh PLL Shut Down
G1/S3 (Suspend-to-RAM) Off Self Refresh PLL Shut Down
G1/S4 (Suspend-to-Disk) Off Off Off
G2/S5 (Soft Off) Off Off Off
G3(Mechanical Off) Off Off Off
Crusoe Processor Typical Power Consumption
-TM5800 367-800 MHz 0.9-1.3V
Processor Performance Voltage Thermal
Model Range Range Power
TM5800-667 MHz 300-667 MHz 0.9 -1.3V 5.0 W
TM5800-700 MHz 333-700 MHz 0.9 -1.3V 5.3 W
TM5800-733 MHz 333-733 MHz 0.9 -1.3V 5.5 W
TM5800-800 MHz 367-800 MHz 0.9 -1.3V 6.0 W
Workload ACPI State Crusoe Processor Core +
Integrated Northbridge
DVD Playback (C0-C3) 1.05 W
MP3 Playback (C0-C3) 0.42 W
Auto Halt (C1) 0.31 W
Quick Start (C2) 0.20 W
Deep Sleep (C3) 0.15 W
Off/Instant On 0.00 W
The above is from
http://www.transmeta.com/pdf/specifications/productbrief_tm5800_05jul01.p=
df
Those ACPI states look very interesting. I've noticed
that there are some advanced ACPI features in both the
peripheral interface chips (super IO) and the modern
PCI devices. The next question becomes, how to shut
down or sleep periherals when not in use. I will be
doing some investigation into this shortly.
-- Doug
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