> Here's the CPU with bus connections. I can't get a hold of a scanner, > so I'm going to try to asciify one page each couple of nights. > __________________ > /RD----| /RD A0|------------+--A0 > /WR----| /WR | | > | A1|----------+----A1 > +--| /WAIT | | | > | | A2|--------+------A2 > +--| /INT | | | | > | | A3|------+--------A3 > Vcc-+--| /NMI | | | | | ______ > | | A4|-A4 | | | +---------|A Y0|--/BANK > +--| /BUSREQ ...|-... | | +-----------|B Y1|--/DISP0 > | A14|-A14 | +-------------|C Y2|--/DISP1 > /CLK---| /CLK | | | Y3|--/KB > /RST---| /RESET | | ____ Vcc-|G1 | > | | +--|OR | | | > | | | |gate|-------|G2 | > | /IORQ|----+----|____| |______| > D0-----| D0 | | | ____ > ...----| ... | | +--|>o--|OR |------------/USER > D7-----| D7 | +---------|____| > | | ____ > | A15|-----------+--|OR | > | | | | |------------/ROM > | /MREQ|---------+----|____| > |__________________| | | ____ > | +--|>o---|OR |------/RAM > +----------|____| > Z80 CPU with bus connections. Glue logic includes 1/3 of a > 74C04 Hex Inverter, 1 74C32 Quad 2-in OR gate, 1 74LS138 > 3to8 line decoder. > (The rest of the inverter is used elsewhere in the circuit, BTW) I'm a low chipcount freak. I might be tempted to glom all the logic in the or gates, inverters, and 3to8 decoder in the right side of the diagram into a single programmable device (PAL? PLA? it's been a while). I believe that's the general approach on today's modern motherboards. An ASIC is programmed/fabbed to do the address decoding. I doubt you'll find many discrete logic gates on a modern motherboard. --Adam -- Subcription/unsubscription/info requests: send e-mail with subject of "subscribe", "unsubscribe", or "info" toWear-Hard Mailing List Archive (searchable): http://wearables.ml.org
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