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Tonight we explore the mysteries of the pseudo-MMU (Let us call it the
Bank Switcher). Yay.
As always, please tell me if you find any bugses.
The part count could indeed be lowered, but I have all of the stuff that
I need to build the thing (except for the RAM and LCD) in my junk
boxes. Trying to use stuff I've already got. Though I DO want to get
into FPGAs eventually...
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____
/BANK-|OR |
|Gate|
/RD---|____|---------------------------+-+-+-+-+-+-+-+
| | | | | | | |
_____________ | | | | | | | |
D0---------------|D0 Q0|--+---|>-----------------D0
| | | | | | | | | |
D1---------------|D1 Q1|----+---|>---------------D1
| | | | | | | | | |
D2---------------|D2 Q2|------+---|>-------------D2
| | | | | | | | | |
D3---------------|D3 Q3|--------+---|>-----------D3
| | | | | | | | | |
D4---------------|D4 Q4|----------+---|>---------D4
| | | | | | | | | |
D5---------------|D5 Q5|------------+---|>-------D5
| | | | | | | | | |
D6---------------|D6 Q6|--------------+---|>-----D6
| | | | | | | | | |
D7---------------|D7 Q7|----------------+---|>---D7
____ | | | | | | | | | |
/WR---|OR |-|>0-|Clock | | | | | | | | |
|Gate| | | | | | | | | | +------BA20
/BANK-|____| | | | | | | | | +--------BA19
| | | | | | +------------BA18
GND--------------|OC | | | | +--------------BA17
|_____________| | | +----------------BA16
| +------------------BA15
+--------------------BA14
RAM Bank switcher using octal latch. Also uses (2) 2-in OR,
(1) Octal Tri-state Buffer (Active Low, but I didn't have
enough room for the "o"s).
Writing a byte to port 0x0 selects which bank. Reading
returns current bank.
Allows addressing up to 2048K of RAM (not 4096 as I said
earlier; oops).
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