This is a multi-part message in MIME format.
--------------4997867DCEBCCEFD5DC6CFC6
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Whew. I'm really glad I'm asciifying this stuff... I've caught and
fixed several bugs already...
So, without further ado, the RAM/ROM:
--------------4997867DCEBCCEFD5DC6CFC6
Content-Type: text/plain; charset=us-ascii; name="z80-wc.3.txt"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="z80-wc.3.txt"
Lots of ORs, huh? Here's the RAM:
_______
BA17--|Big |
BA18--|OR |
BA19--|Gate |-----------------------------+
BA20--| | |
/RAM--|_______| |
__________ |
| /CE|--+
| /OE|--/RD
A0--|A0 /WE|--/WR
...--|... |
A14--------------+ A13--|A13 |
| | D0|--D0
| ____ | ...|--...
BA14---------------|OR |-----|A14 D7|--D7
+-|____| | |
| ____ | |
BA15---------------|OR |-----|A15 |
+-|____| | |
| ____ | |
BA16---------------|OR |-----|A16 |
+-|____| |__________|
Ok, wierdness needed to keep the banked and non-banked
RAM on the same chip. A15 (on the bus) is irrevelant
A14 will be low when non-banked is accessed, and high
when banked is accessed, so the OR gates make A14-16
(on the chip) stay low when A14 is low, but let BA
lines through when A14 is high. If you don't plan
on adding any RAM beyond the initial 128K, you can
axe the Big OR Gate (as well as part of the bank
switcher).
ROM:
_________
A0----|A0 /CE|---/ROM
...---|... /OE|---/RD
A14---|A14 /PGM|---Vcc
| UPP|---Vcc
D0----|D0 |
...---|... |
D7----|D7 |
|_________|
That wasn't quite as confusing as the RAM, eh?
--------------4997867DCEBCCEFD5DC6CFC6--
--
Subcription/unsubscription/info requests: send e-mail with subject of
"subscribe", "unsubscribe", or "info" to 
Wear-Hard Mailing List Archive (searchable): http://wearables.ml.org
From Wear-Hard Mailing list Archive (WH)
Maintained by R. Paul McCarty
Archive created with babymail